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Core1553BRT v4.0 Handbook
Interrupt Vector Extension
The core generates a 7-bit interrupt vector that contains the subaddress and whether it was a transmit or
receive message. Some systems may need to include whether the message was a broadcast, a mode
code, or the actual word count in the interrupt vector. The core supports an interrupt vector extension
function, similar to the address mapper function using the INTLAT signal, as shown in Figure 5-3 .
CMDVAL
CLK1553
INTLAT
D SET Q
L CLR Q
INTVECT
Interrupt
Vector
Extender
Extended
Interrupt
Vector
Figure 5-3 ? Interrupt Vector Extension
Status Word Settings
Core1553BRT sets bits in the 1553B status word in compliance with MIL-STD-1553B. This is
summarized in Table 5-2 .
Table 5-2 ? Status Word Bit Settings
Bit(s)
15:11
10
9
8
7:5
4
3
2
1
0
Function
RT Address
Message Error
Instrumentation
Service Request
Reserved
Broadcast Received
Busy
Subsystem Flag
Dynamic Bus Acceptance
Terminal Flag
Setting
Equals the RTADDR input.
Set whenever the RT detects a message error.
Always 0
Controlled by the SREQUEST input.
Always 000.
Set whenever a broadcast message is received.
Controlled by the RTBUSY input.
Controlled by the SSFLAG input.
Always 0. Core1553BRT does not operate as a bus controller.
Controlled by the TFLAG input. If an “inhibit terminal flag” mode
code is in effect, will be 0.
Command Word Storage
At the start of every 1553B bus transfer, the 1553B command word is written to RAM locations 000–01F
for receive operations and 3E0–3FF for transmit operations. The address used is as follows:
?
?
CMD location, RX commands: '000000' and SA
CMD location, TX commands: '011111' and SA
If the RT is implemented without a memory-based backend, the writing of the command word can be
disabled (WRTCMD input). This simplifies the design of the backend logic that directly controls the
backend function.
Revision 3
29
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